• Date：Jun 02, 2026
• Location： San Jose, CA, USA

Solve what breaks in semiconductor packaging—before it reaches production

Join a focused, small-group forum on eliminating voids, controlling fillet and overflow, and reducing warpage through simulation-driven insight.

Semiconductor packaging teams are under increasing pressure to deliver smaller, faster, and more reliable devices—across both traditional transfer molding and advanced processes such as underfill, potting, and encapsulation—driven in part by emerging architectures like HBM, chiplet-based designs, and AI-focused applications. Yet critical issues such as void formation in underfill and encapsulation, fillet control, overflow, wire sweep, and package warpage are often only discovered late in development—leading to costly iterations, qualification delays, and reliability risks.

This half-day, in-person forum brings together industry experts to explore how these challenges can be addressed earlier through simulation-driven approaches. Hosted by Moldex3D, the sessions will highlight how combining process simulation with structural and multiphysics analysis provides deeper visibility into encapsulation behavior, stress development, and long-term package reliability—before tooling and production.

Through real-world case studies and technical discussion, attendees will learn how to:
• Predict and reduce voids, fillet inconsistencies, overflow, and wire sweep in underfill, potting, encapsulation, and transfer molding processes
• Understand and mitigate warpage and residual stress to improve package integrity and yield
• Reduce design iterations and qualification cycles to accelerate development and lower cost

This is a focused, small-group event designed for practical learning and open discussion with peers facing similar challenges.

Agenda

Venue

Holiday Inn San Jose Silicon Valley
1350 North First Street, San Jose,  CA 95112

Contact

Srikar Vallury
E: sales.us@moldex3d.com
P: 248-946-4570